The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a high withstand voltage transistor constituting a peripheral circuit of a flash or an electrically erasable and programmable read only memory (EEPROM) which is a nonvolatile memory device operating at high voltage, and a method for manufacturing the same.
In a semiconductor device using a nonvolatile memory, a memory cell is driven by charging or discharging a floating gate with an electrode by supplying a high voltage signal to each node of a storage cell. In general, the high voltage is generated by a boosting circuit inside a chip with a single power supply Vcc. The boosting circuit comprises transistors having excellent voltage withstanding characteristics. The high voltage signal generated by the boosting circuit has a pulse shape and is supplied to each node of a memory cell, thereby changing the state of the memory cell. Accordingly, the voltage for driving the cell is limited by the peripheral boosting circuit. In general, a transistor constituting a boosting circuit should have a withstand voltage characteristic which is higher than the operating voltage for a nonvolatile memory cell.
In general, a high withstand voltage transistor is determined by the following four factors:
first, the point at which the insulation of the gate insulating film between the gate and the drain and between the gate and the source breaks;
second, a junction breakdown between the drain and the substrate;
third, a junction breakdown between the gate electrode and the drain due to concentration of an electrical field; and
fourth, the punchthrough characteristics between the source and the drain.
The strength of the electrical field necessary to breakdown the insulating film is fairly consistent and the strength becomes greater in proportion to the thickness of the gate insulating film. Accordingly, to increase the voltage withstand of the gate insulating film, the gate insulating film should be made thicker. For example, a 500 .ANG. oxide film can withstand voltages of 30.about.50V. When the gate insulating film is formed thicker, the threshold voltage of the transistor is increased. Here, in order to maintain the threshold voltage at an appropriate level, the impurity concentration implanted into the channel region should be lowered, which weakens the punchthrough characteristics.
The junction breakdown between the drain and the substrate is proportional to the thickness of the depletion layer formed between the substrate and the drain. That is, as the depletion layer becomes thicker, the tendency for the insulation to breakdown becomes higher. The thickness of the depletion layer is determined by the concentration of the impurity implanted into the substrate and the drain.
The junction breakdown due to the concentration of the electrical field between the gate electrode and the drain is generated at a surface of the drain facing the gate electrode since diffusion of the depletion layer is restrained by the pn-junction. Accordingly, the withstand voltage characteristics at the junction of the drain and the gate electrode is lowered to generate the breakdown at a lower voltage than the withstand voltage at the junction. Here, in general, a drain region having a lower impurity concentration, called a lightly doped drain (LDD), at which the junction withstand voltage is higher than that of a usual drain part is formed and the concentration of the gate electrical field is restricted to the LDD, to prevent lowering of the withstand voltage at the surface.
The punchthrough between the drain and the source is generated by the diffusion of the depletion layer to the source region caused by a high voltage supplied to the drain region. Here, in order to prevent punchthrough, the distance between the source and the drain can be broadened. However, this leads to an increase in the area of the device, thereby preventing integration of the memory cell. The punchthrough can also be prevented by restraining the diffusion of the depletion layer by increasing the impurity concentration of the channel.
In general, in a high voltage transistor, a deep n-junction is formed on a p-type substrate by implanting phosphorus ions having the form of a donor at low concentration into source and drain regions at high energy. The gate insulating film is formed thicker than that of a low voltage transistor used for logic circuits.
However, diffusion of the depletion layer in the direction of the channel during the deep junction formation causes lowering of the punchthrough characteristic. Punchthrough is also generated by a phosphorus region of low concentration which surrounds the region implanted by arsenic (As) ions of high concentration. The threshold voltage of a transistor is increased by using a thick insulating film. However, the characteristic of punchthrough is lowered when lowering the concentration of an impurity implanted into the channel region in order to maintain the threshold voltage at an appropriate level.
In a conventional method for improving punchthrough and breakdown characteristics in a high withstand voltage transistor (see U.S. Pat. No. 5,061,649 "Field Effect Transistor with Lightly Doped Drain Structure and Method for Manufacturing the Same"), the gate insulating film is formed thick, and, further, the impurity concentration of the channel is formed at low concentration to obtain an appropriate threshold voltage, which lowers the punchthrough characteristic. The breakdown voltage is increased, since source and drain regions form a deep junction with a low impurity concentration so that scaling down of the channel length is hindered.
A conventional method for manufacturing the high withstand voltage transistor can be described as follows.
FIG. 1 is a sectional view of a high withstand voltage transistor manufactured by the conventional method. In detail, field oxide film 3 for isolating the device is formed on p-type substrate 1, and a channel stop region formed of an impurity of the same kind as that of the substrate is located under field oxide film 3. A channel region is formed by ion-implanting the same kind of impurity as that of the substrate to control a threshold voltage. Then, thick gate insulating film 5 is formed on the substrate, and further, polysilicon and silicide are sequentially deposited on gate insulating film 5 and patterned to form gate electrode 7. Phosphorus is ion-implanted at high energy using gate electrode 7 as a mask to form deep junction impurity regions, 9 and 9a, at low concentration. Spacers 11 for gate electrode 7 are formed by depositing an insulating layer on the surface of the resultant structure from above and etching back the insulating layer. Then, impurity layers 13 and 13a are formed on source and drain regions by ion-implanting arsenic at high concentration using spacers 11 as a mask to lower contact resistance. Subsequently, an interlayer dielectric film 15 is deposited on the whole surface of the resultant structure, and planarized by reflowing. Interlayer dielectric film 15 is patterned to form a contact hole to the source and drain regions. A metal electrode is formed by filling the contact hole with metal 17, to thereby complete the high withstand voltage transistor.
In the conventional method for manufacturing the high withstand voltage transistor, a thick insulating film is formed, and the impurity concentration of the channel is lowered to obtain an appropriate threshold voltage. However, this lowers the punchthrough characteristic. Also, in order to increase the breakdown voltage, source and drain regions form a deep junction with low impurity concentration, which hinders scaling down of the channel length.